The present invention relates generally to integrated circuit design revision management, and more particularly, initial repetition of a novel base cell design and routing for reducing layers revisions in Engineering Change Orders (ECOs).
Demands of consolidating functions and applications from printed circuit board to a single chip are growing stronger. These demands have made the scales and designs of integrated circuit (IC) increasingly complex and time consuming. Computer-Aided Design (CAD) has become a necessary tool to speed up and improve the quality of IC design. Of all the phases in designing application specific integrated circuit (ASIC), physical layout takes up a major portion of the design cycle.
In creating a physical layout of an ASIC, a computer layout may be first generated. Generally, the computer layout may be created by arranging a number of individual blocks or “logic cells” based on designated schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized cell design. Such cell design techniques can save time in design cycle, as it may be no longer necessary for an IC designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells appropriately to generate a circuit that performs a desired function. Each of the logic cells contains a number of terminals for implementing into the IC.
To release the layout to a mask making for semiconductor processing, the data is loaded in a tape, and is given to a mask shop. This is called tape-out. To tape-out such a computer layout, commercial place-and-route CAD tools are used. More particularly, place-and-route CAD programs are used 1) to arrange logic cells and other elements to optimize their interconnections and the overall size and 2) to define the routing region and to select channels to connect the logic cells and elements. A place-and-route CAD tool requires as input a predetermined number of predefined logic cell types (e.g., Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, Decap, etc.) to implement the tasks mentioned above. In response, the place-and-route CAD tool outputs a computer layout.
Using the computer layout generated as a blueprint, a number of basic CMOS transistor layers, contact, and metal layers defining the elements and interconnections of the IC are created in silicon through a combination of semiconductor processes namely depositing, masking, and etching. When combined, these layers form the IC with functions. Depending on the complexity of the ASIC, each circuit may involve multiple basic layers, multiple contacts, and multiple metal layers. This layer-patterns-release procedure is widely known as tape-out.
Following tape-out, for various reasons including design changes, modifications are subsequently required to delete as well as add logic elements and interconnections from the original design. When this occurs, an engineering change order (ECO) is generated to document the desired changes. Next, the computer layout generated earlier is modified using the commercial place-and-route CAD tool to incorporate the desired changes. Under Conventional methods, extra logic cells of different types are included in the original computer layout as reserves in case new elements are needed. However, due to limitations inherent in the software environment (e.g., capability to handle a limited number of variables), the place-and-route CAD tool requires that these extra logic cells be of predefined types and numbers. Because the types of the logic cells are predefined as Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, Decap, etc., modifications are limited to changing the logic cells connectivity. Such inflexibility may cause negative consequences. For embodiment, in adding logic elements as required under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function must be deleted or the process of generating a computer layout with the desired logic cells must be restarted. As such, neither one of these options is desirable.
Even if the right type logic cells are available for adding, the layout engineer must still make the proper connections. Because the locations of the logic cells are fixed, it is sometimes not possible to provide the desired connections given existing obstacles and various space constraints in the layout. In addition, it is a painful and time-consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells. Because of the increasing complexity of IC design and modification, the turn-around time to incorporate the desired ECO changes is generally high.
When what is desired is a shorter product life cycle that pushes time-to-market shorter, multimillion dollar and lengthy design cycle of high resolution mask revision become intolerable.
What is desired is a methodology and an ECO base cell that can be used for revising the same to accommodate design change.